Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism

Published on September 12, 2023

Just like the human brain filters out irrelevant information, researchers have developed a brain-inspired hybrid-grained scrubbing mechanism to tackle soft errors in SRAM-based field programmable gate arrays (FPGAs). These errors can corrupt the configuration memory of FPGAs, affecting their performance. The proposed mechanism includes fine-grained and coarse-grained scrubbing to quickly mitigate and repair errors after a single-event upset (SEU) occurs. By utilizing targeted scrubbing of specific frames or modules, this mechanism achieves precise error location and recovery, surpassing other approaches in error recovery time and hardware overhead. The effectiveness of this mechanism has been demonstrated through fault injection campaigns on benchmark circuits. It effectively mitigates and repairs both single-bit upsets (SBUs) and double-bit upsets (DBUs), enhancing the reliability of SRAM-based FPGAs. To explore this exciting research further, check out the full article!

Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this kind of error, this study proposes a brain-inspired hybrid-grained scrubbing mechanism consisting of fine-grained and coarse-grained scrubbing to mitigate and repair the errors as quickly as possible after an SEU occurrence. Inspired by the human brain’s ability to filter out redundant and irrelevant information, we propose a mechanism that can mask invalid position information when errors occur. Compared with the scrubbing of full configuration memory, this mechanism can achieve precise error location and recovery utilizing targeted scrubbing of specific frames or modules. The effectiveness is evaluated by executing fault injection campaigns on the International Symposium on Circuits and Systems 1989 (ISCAS89) benchmark circuits and fault tolerant fast Fourier transform (FT-FFT) circuit. If upsets are detected, they will be repaired with fine-grained or coarse-grained scrubbing depending on their location. The experiment results show that this mechanism can effectively mitigate and repair single-bit upsets (SBUs) and double-bit upsets (DBUs). In addition, the mechanism is proven to be superior in error recovery time and hardware overhead compared to counterpart approaches.

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